>>Опа, x87 или SSE уже никатит? :)
>Так скорость нужна или нет? На GPU для этого параллельные конвейеры.
>>как эту хрень распределить по процам???
>А если серьёзно в коде нельзя указать на каком CPU работать
>Но можно создать процессы (разные CPU, память, стек; один код), и потоки
>(разные CPU, стек; один код и память). Язык значения не имеет. Опа, оказывается x86 настолько корявый....
8.4.4.1 Typical BSP Initialization Sequence
After the BSP and APs have been selected (by means of a hardware protocol, see
Section 8.4.3, “MP Initialization Protocol Algorithm for Intel Xeon Processors”), the
BSP begins executing BIOS boot-strap code (POST) at the normal IA-32 architecture
starting address (FFFF FFF0H). The boot-strap code typically performs the following
operations:
1. Initializes memory.
2. Loads the microcode update into the processor.
3. Initializes the MTRRs.
4. Enables the caches.
5. Executes the CPUID instruction with a value of 0H in the EAX register, then reads
the EBX, ECX, and EDX registers to determine if the BSP is “GenuineIntel.”
6. Executes the CPUID instruction with a value of 1H in the EAX register, then saves
the values in the EAX, ECX, and EDX registers in a system configuration space in
RAM for use later.
7. Loads start-up code for the AP to execute into a 4-KByte page in the lower 1
MByte of memory.
8. Switches to protected mode and ensures that the APIC address space is mapped
to the strong uncacheable (UC) memory type.
9. Determine the BSP’s APIC ID from the local APIC ID register (default is 0), the
code snippet below is an example that applies to logical processors in a system
whose local APIC units operate in xAPIC mode that APIC registers are accessed
using memory mapped interface:
MOV ESI, APIC_ID; Address of local APIC ID register
MOV EAX, [ESI];
AND EAX, 0FF000000H; Zero out all other bits except APIC ID
MOV BOOT_ID, EAX; Save in memory
Saves the APIC ID in the ACPI and MP tables and optionally in the system config-
uration space in RAM.
10. Converts the base address of the 4-KByte page for the AP’s bootup code into 8-bit
vector. The 8-bit vector defines the address of a 4-KByte page in the real-address
mode address space (1-MByte space). For example, a vector of 0BDH specifies a
start-up memory address of 000BD000H.
11. Enables the local APIC by setting bit 8 of the APIC spurious vector register (SVR).
MOV ESI, SVR; Address of SVR
MOV EAX, [ESI];
OR EAX, APIC_ENABLED; Set bit 8 to enable (0 on reset)
MOV [ESI], EAX;
12. Sets up the LVT error handling entry by establishing an 8-bit vector for the APIC
error handler.
MOV ESI, LVT3;
MOV EAX, [ESI];
AND EAX, FFFFFF00H; Clear out previous vector.
OR EAX, 000000xxH; xx is the 8-bit vector the APIC error handler.
MOV [ESI], EAX;
13. Initializes the Lock Semaphore variable VACANT to 00H. The APs use this
semaphore to determine the order in which they execute BIOS AP initialization
code.
14. Performs the following operation to set up the BSP to detect the presence of APs
in the system and the number of processors:
— Sets the value of the COUNT variable to 1.
— Starts a timer (set for an approximate interval of 100 milliseconds). In the AP
BIOS initialization code, the AP will increment the COUNT variable to indicate
its presence. When the timer expires, the BSP checks the value of the COUNT
variable. If the timer expires and the COUNT variable has not been incre-
mented, no APs are present or some error has occurred.
15. Broadcasts an INIT-SIPI-SIPI IPI sequence to the APs to wake them up and
initialize them:
MOV ESI, ICR_LOW; Load address of ICR low dword into ESI.
MOV EAX, 000C4500H; Load ICR encoding for broadcast INIT IPI
; to all APs into EAX.
MOV [ESI], EAX; Broadcast INIT IPI to all APs
; 10-millisecond delay loop.
MOV EAX, 000C46XXH; Load ICR encoding for broadcast SIPI IP
; to all APs into EAX, where xx is the vector computed in step 10.
MOV [ESI], EAX; Broadcast SIPI IPI to all APs
; 200-microsecond delay loop
MOV [ESI], EAX; Broadcast second SIPI IPI to all APs
; 200-microsecond delay loop
Step 15:
MOV EAX, 000C46XXH; Load ICR encoding from broadcast SIPI IP
; to all APs into EAX where xx is the vector computed in step 8.
16. Waits for the timer interrupt.
17. Reads and evaluates the COUNT variable and establishes a processor count.
18. If necessary, reconfigures the APIC and continues with the remaining system
diagnostics as appropriate.
